Location:- Boxborough,MA
Hourly Pay Rate Range - $55.00 - $70.00 /HR (Depending on working experience)
Note:- this is not junior/intermediate role must have minimum 7+ years of industrial experience as RTL Design Engineer
The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues
PREFERRED EXPERIENCE:
• Digital design engineering experience
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Strong understanding of computer organization/architecture.
• Mixed signal RTL experience is a plus
ACADEMIC CREDENTIALS:
• Bachelors or Masters degree in computer engineering/Electrical Engineering
Employee Benefits:
At LanceSoft, full time regular employees who work a minimum of 30 hours a week or more are entitled to the following benefits:
Four options of medical
Insurance
Dental and Vision
Insurance
401k Contributions
Critical Illness
Insurance
Voluntary Permanent Life
Insurance
Accident Insurance
Other Employee Perks
About LanceSoft
LanceSoft is rated as one of the largest staffing
firms in the US by SIA. Our mission is to establish global cross-culture human connections that further the careers of our employees and strengthen the businesses of our clients. We are driven to use the power of our global network to connect businesses with the right people, and people with the right businesses without bias. We provide Global Workforce Solutions with a human touch.
EEO Employer
LanceSoft is a certified
Minority Business Enterprise (MBE) and an equal opportunity employer. We
prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state ,or local laws.
This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.
Want to read more about LanceSoft?
Click here to visit our website - www.lancesoft.com