Memory Layout Design: Design and implement memory arrays, peripheral circuits, and associated elements for SRAM, DRAM, Flash, or other memory technologies using industry-standard EDA tools.

DRC/LVS/RCX Compliance: Perform Design Rule Checks (DRC), Layout Versus Schematic (LVS) checks, and resistance/capacitance extraction (RCX) to ensure that layouts meet process specifications and design requirements.

Area and Power Optimization: Optimize memory cell layouts for area, performance, and power consumption. Strive for the smallest possible footprint while meeting all functional and performance specifications.