Location: Remote (India-based preferred)
Experience: 8+ years in Memory Design
Job Overview:
We are looking for a Memory Design Lead to drive a long-term (3–4 years), cluster-level memory project from scratch to tapeout. This is a remote opportunity where you will be responsible for leading and managing a team of 5–8 engineers. You’ll be at the forefront of designing high performance, low-power SRAMs and memory subsystems for next-gen SoCs, ensuring robust execution across all design phases—from specification to silicon.
Key Responsibilities:
• Architect and lead the end-to-end design of custom SRAM blocks and memory clusters.
• Manage a team of 5–8 engineers across design, verification, and validation.
• Own the full project lifecycle: spec definition, design, verification, sign-off, and tapeout.
• Collaborate closely with analog, digital, layout, and process technology teams.
• Ensure timely delivery with optimal performance, area, and power trade-offs.
• Guide team in debugging silicon issues and supporting post-silicon validation.
• Drive project execution with milestones aligned to long-term program goals.
Qualifications:
• Bachelor’s/Master’s in Electrical or Electronics Engineering.
• 8+ years of hands-on memory design experience, particularly SRAM-based architectures.
• Proven expertise in RTL-to-GDS flow, memory compilers, and sign-off tools.
• Experience leading teams in cluster-level SoC/memory subsystem development.
• Strong knowledge of EDA tools (Cadence/Synopsys), simulations, and PPA optimization.
• Excellent technical leadership, mentoring, and communication skills.
Preferred Skills:
• Experience with FinFET and advanced node technologies (7nm and below).
• Familiarity with ISO26262 (automotive safety) standards.
• Exposure to embedded NVM, ROMs, or DRAM-based systems.