Job Details: Job Description: You will be part of the Corporate Memory Organization Memory Compiler Team and will own significant engineering tasks in a fast-paced and technically challenging environment. Job function involves understanding and converging SRAM designs to specific process and product needs, defining PV methodology, collaborating with Mask Design teams on layout. The role involves circuit design tasks ranging from technical readiness, bit-cell simulation studies, critical path simulations, schematic entry, running design verification with industry and in-house PV tool suites. You will be involved in methodology definition tasks as well as executing project schedules. Responsibilities of the role include but are not limited to: * Provide design solutions for meeting challenging memory design specs for various product segments. Memory Compiler Design, Flow and Methodology development. * Design, validation, and characterization of SRAM Compilers. * Interfacing with customers. In addition to the qualifications listed above, the ideal candidate will also demonstrate: * SRAM circuit design * Timing convergence and circuit quality metrics such as noise, power, reliability * Solid fundamental knowledge of transistor level behavior and device characteristics. * Scripting knowledge. * Logical thinking, analytical and problem-solving skills. * Verbal/written communication skills. Interpersonal skills. * Multitasking/prioritization skills. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: * Candidate must have a Master's degree in electrical engineering with 5-10+ years of experience in Memory design related field. * 5+ years of experience in the following: * Thorough understanding of SRAM operations. * Transistor level operation (VLSI course work), design challenges under process variations and low power circuit technique. Preferred Qualifications: * Ph.D. in electrical engineering with 5+ years of experience in Memory design related field. * Scripting (Perl or tcl or Python, etc.) Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and/or schoolwork, classes, and research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003 Annual Salary Range for jobs which could be performed in the US: $161,230.00-$227,620.00 Salary range dependent on a number of factors including location and experience. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.