Lumotive’s award-winning optical semiconductor solutions enable advanced sensing and perception capabilities in next-generation consumer, mobility, and industrial automation products such as mobile devices, autonomous vehicles, and robots. The company’s patented Light Control Metasurface (LCM™) beam steering chips deliver an unparalleled combination of high performance, exceptional reliability, and low cost — all in a tiny, easily integrated solution. Lumotive has received measurable industry acclaim including Laser Focus World's 2024 Innovators Award; CES Innovation Awards in 2022, 2024, and 2025; Fast Company’s Next Big Thing in Tech 2023; a 2022 SPIE PRISM Award; and a prestigious Edison Award. Investors include Gates Frontier, MetaVC Partners, Quan Funds, Samsung Ventures, and Uniquest.

Job Description:

Lumotive is seeking a talented and experienced ASIC Design Engineer to lead the design and implementation of Beam steering Mixed Signal ASIC Controllers. The ideal candidate is a self-motivated and quick learner who thrives in a fast-paced, cross-functional environment and brings deep expertise in RTL design for mixed-signal SoCs.

Responsibilities:

• Design and implement RTL for complex Mixed Signal ASIC SoCs
• Develop and integrate ARM-based processor subsystems and SoC interconnect fabrics
• Drive architecture, microarchitecture, and RTL development of digital logic blocks
• Collaborate closely with analog/mixed-signal, verification, DFT, and physical design teams
• Perform logic synthesis, DFT insertion, STA, and generate timing constraints
• Run and resolve issues from LINT, CDC, and Formal Verification tools
• Support post-silicon validation and bring-up activities as needed
  
  
  

Qualifications:

• BSEE or MSEE in Electrical Engineering or related field
• 5+ years of hands-on experience in RTL design, preferably in Display Controllers, Touch Controllers, Wired/Wireless Communication Systems and Automotive Sensor Communication Systems
• Strong experience in developing ARM-based processor subsystems and SoC fabrics
• Strong expertise in Verilog and SystemVerilog
• Solid understanding and practical experience with CDC (Clock Domain Crossing), LINT tools, Synthesis, Formal Verification, and Static Timing Analysis (STA)
• Experience with design for testability (DFT), scan insertion, and ATPG
• Proficiency in scripting languages such as Python or Perl
• Experience working at both block-level and full-chip integration
• Experience in DSP (Digital Signal Processing) design
• Knowledge of analog/mixed-signal interaction and integration
• Familiarity with industry-standard EDA tools (Synopsys, Cadence, Siemens/Mentor)
• Experience in low-power design techniques
  
  
  

Benefits include but not limited to:

Health, dental and vision

FSA, HSA

PTO plus 14 paid company holidays

401K with 3% contribution

Stock Options

Daily lunch and snacks

Life insurance and disability

Base pay is scaled depending on experience + Performance based Quarterly Bonus + Equity.