Role Purpose:

SOC Implementation Engineer (SoC/Block)

Experience- 10+ years

Notice Period- Immediate to 45 days

Responsibilities:

• Lead the top-level/block-level implementation of SoC designs, including IO ring integration.
• Perform SoC/Block-level synthesis, including different hard macros.
• Design IO rings based on specifications.
• Handle DFT insertion, OCC, compressor insertion, ATPG pattern generation, and simulations.
• Conduct SoC/Block-level formal verification.
• Execute SoC/Block-level place & route (PnR) and timing analysis.
• Perform floorplanning, placement, routing, and timing closure.
• Run SoC/Block-level LVS and DRC in ST P18/P28 technology.
• Debug and resolve complex design issues in collaboration with other engineering teams.
• Conduct design reviews and provide technical guidance to team members.

Skills & Expertise:

• Collaborate with the design team for hard IP and SoC top-level implementation.
• Utilize Synopsys Fusion Compiler for physical and WLM synthesis.
• Perform timing analysis and resolve timing issues.
• Execute place and route flows using Cadence Innovus and Synopsys Fusion Compiler.
• Implement FlipChip SoC designs, including RDL routing.
• Ensure timing and design signoff (STA, LVS, DRC).
• Work with tools such as Synopsys Design Compiler, DFT Compiler, PrimeTime, Cadence Innovus, and Mentor Graphics Calibre.

Must-Have Skills:

• Experience with place & route flows using Innovus or Fusion Compiler.
• Expertise in chip-level and block-level design implementation.
• Strong knowledge of IO ring design and analysis.
• Experience in timing and design signoff.