Title: Layout Designer

Industry: Tech

Location: Cupertino, CA (Remote)

Duration: 12 months

Responsibilities:

• Design and deliver complex layouts for analog and mixed-signal circuits, including PLLs, ADCs, DACs, LDOs, amplifiers, and high-speed interfaces.
• Interpret schematics and floorplans to meet performance, area, and power targets.
• Analyze and optimize floorplans for performance, routability, and manufacturability.
• Perform physical verification checks (DRC, LVS, ERC) and ensure fast closure.
• Collaborate with circuit designers to understand critical intent, negotiate trade-offs, and meet milestones.
• Use industry-standard EDA tools and methodologies in advanced nodes (7nm, 5nm, and beyond).
• Maintain thorough documentation, version control, and enable layout reuse.
• Identify and resolve physical design bottlenecks proactively.
• Apply advanced knowledge of parasitic effects, matching, symmetry, shielding, and routing best practices.

Requirements:

• Minimum 5 years of hands-on experience in analog/mixed-signal layout design in deep sub-micron CMOS processes.
• At least 2 years of experience in FinFET nodes (7nm, 5nm, 3nm).
• Strong expertise in EDA tools like Cadence Virtuoso, Mentor Calibre, Synopsys Custom Compiler; familiarity with digital APR tools like Innovus is a plus.
• Solid understanding of physical verification (LVS/DRC/ERC), parasitic extraction, and reliability analysis.
• Familiarity with scripting languages (SKILL, Python, Perl) for automation.
• Excellent communication and collaboration skills across disciplines.
• Experience with RF, high-speed I/O, or power management layout is a plus.
• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.

Hourly rate is commensurate with experience and is an estimated range provided by WorkGenius.