Location: Austin, TX or Chicago, IL, USA

About Our Client:

Our client is a leading technology-focused firm at the forefront of ultra-low latency high-frequency trading. They specialize in electronic market making, building cutting-edge hardware solutions to gain a critical competitive edge in the world's fastest markets. This is an opportunity to join a small, agile team and contribute directly to FPGA strategies that move significant capital, pushing the boundaries of performance to capitalize on fleeting market opportunities where your hardware innovations directly translate to tangible trading advantages.

The Role:

Are you a latency obsessed FPGA Engineer ready to architect and implement hardware solutions that annihilate nanoseconds and define trading performance? Join our cutting-edge high-frequency trading firm in either Austin, TX or Chicago, IL. As an FPGA Engineer, you will be responsible for the end-to-end lifecycle of custom FPGA-based solutions for processing and acting upon real-time market data, with an unwavering focus on achieving absolute minimum latency. This role demands a deep mastery of hardware design principles, expert proficiency in VHDL and/or Verilog, and a burning passion for conquering complex, timing-critical challenges. You will collaborate closely with our small team of experts, directly contributing to the core of the trading infrastructure.

Key Responsibilities:

• Design, develop, and implement custom FPGA logic in VHDL and/or Verilog for ultra-low latency processing of market data and order generation, with a relentless focus on shaving every nanosecond of latency.
• Implement critical components of our client's ultra-low latency trading pipeline directly in hardware on the FPGA, including physical layer processing, MAC integration, sophisticated packet filtering and instrument data selection, and high-speed payload extraction of relevant order information.
• Develop and implement exchange-specific order formatting and encoding, with expertise in Simple Binary Encoding (SBE), Protocol Buffers, and custom binary formats.
• Implement robust safety mechanisms such as order rate limiting and price bounds directly in hardware.
• Develop and manage a custom, low-latency TCP stack within the FPGA.
• Design and implement the output MAC for ultra-low latency order transmission.
• Take full ownership of the entire development lifecycle, including rigorous testing and verification of your own code using advanced simulation and hardware testing methodologies.
• For critical paths, guide the implementation tools through manual placement of specific logic elements or regions.
• Utilize commands to fine-tune specific optimization parameters for maximum performance.
• Work closely with strategy developers to deeply understand trading strategies and translate them into efficient, ultra-low latency hardware implementations.
• Profile and debug complex FPGA designs to pinpoint and resolve critical timing issues, pushing timing constraints to their absolute limits.
• Develop and maintain custom IP blocks meticulously optimized for ultra-low latency, avoiding or significantly modifying vendor-provided IP.
• Contribute to rapid development cycle, enabling swift deployment and observation of code changes' impact on trading performance.
• Collaborate effectively within a small, agile team, contributing to architectural discussions and proactive problem-solving.
• Stay at the forefront of the latest FPGA technologies and development tools.
• Contribute to the development and maintenance of state-of-the-art FPGA development and testing infrastructure.

Qualifications and Experience:

• Bachelor's or Master's degree in Electrical Engineering.
• Proven experience designing and implementing complex FPGA designs using VHDL and/or Verilog for high-performance applications.
• Deep understanding of digital design principles, advanced timing analysis, and cutting-edge optimization techniques for ultra-high-speed systems.
• Demonstrated experience with industry-standard FPGA development tools (e.g., Xilinx Vivado).
• Solid understanding of networking protocols (Ethernet, TCP/IP) and experience implementing network functionalities within FPGAs (e.g., MAC, packet processing).
• Experience implementing or working with Simple Binary Encoding (SBE) or Protocol Buffers in hardware.
• Demonstrated ability to thoroughly test and debug FPGA designs using advanced simulation and hardware testing equipment.
• Excellent problem-solving and analytical skills.
• Ability to thrive in a high-octane, collaborative team environment.

Desirable Skills and Experience:

• Strong communication skills.
• Highly Desirable: Proven experience optimizing FPGA designs for ultra-low latency, including expert-level timing constraint management (Expert-Level XDC) and physical implementation techniques (floorplanning, placement constraints).
• Experience implementing network-related functionalities within FPGAs (e.g., MAC, packet processing).
• Experience with implementing exchange-specific protocols in hardware.
• Familiarity with high-performance computing architectures and low-latency design principles.
• Experience with scripting languages for automation (e.g., Python, Tcl).
• Personal Attributes:
• A relentless passion for conquering ultra-low latency performance.
• A scrupulous and detail-oriented approach to design and testing.
• Thrives in a high-octane and demanding environment.
• A proactive and self-starting attitude.
• A creative problem-solver willing to explore unconventional design solutions to annihilate latency.

Notes:

Not considering SOC/ASIC engineers, remote FPGA engineers, or FPGA engineers in large teams. FPGA Engineers working on high speed network functionalities are of specific interest. FPGA engineers who have done some work on ASIC are of interest.