Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off. The Responsibility also includes supporting design verification to tapeout. Duties / Qualifications: BSEE is required, MSEE is preferred. Strong understanding of digital circuit design and EE concepts Logic design experience using Verilog. Experience with architecture, specs, documentation, coding in Verilog and debugging. Experience in full IC project flows Knowledge in verification processes