Hello Connections

Greetings from Tessolve Semiconductors!!

Design and Verification Engineer

Verification Engineer/Sr. Engineer/Lead/Managers – ASIC/IP/SOC/CPU (Design Verification )

Location : India/Abroad

Experience - 7+

• IP verification Using SV/UVM

• SOC Verification using C/SV

• Third Party VIP Integration

• Interconnect Protocols: AHB, AXI, APB

• SOC Interfaces: GPIO, SPI, I2C, UART (5+)

• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)

• Memory Interfaces: DDR or HBM I/O (10+)

• Coverage Closure: Code, Functional and Toggle

• Tools: Synopsys VCS or Cadence Incsive

• Technical Documentation: Testbench Specification, Test Plan Specification

• Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Please share your CV to sushma.siddaroda@tessolve.com