Skygate Consulting

Design Verification Engineer - System Verilog/UVM

Noida, UP, IN

26 days ago
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Summary

Job Title : CPU/IP Subsystem Verification Engineer 5+ Years Experience

Location : Bangalore / Pune / Noida

Job Type : Full-Time

Key Responsibilities

  • Develop and implement verification plans and strategies for CPU/IP subsystems based on design and architecture specifications.
  • Build and maintain System Verilog/UVM-based testbenches for block-level and subsystem-level verification.
  • Write and execute constrained-random and directed test cases to verify functionality and ensure corner case coverage.
  • Drive functional coverage closure, develop assertions, and debug simulation failures.
  • Collaborate with RTL designers, architects, and software teams to root-cause and resolve design issues.
  • Automate regression environments using scripting languages (Python, Perl, or Shell).
  • Participate in design and verification reviews to ensure comprehensive coverage and design quality.

Preferred Qualifications

  • Exposure to RISC-V or ARM CPU architectures.
  • Experience with formal verification tools and techniques.
  • Familiarity with emulation/FPGA-based validation is a plus.
  • Knowledge of performance/power-aware verification methodologies.

(ref:hirist.tech)

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