Verification Engineer

Contract/Contract to Hire

On site in Sunnyvale, CA or Austin, TX

Pay Rate: $75-$85/hour (W2)

Mandatory Experience:

• 7+ years experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
• Experience in the development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs

Minimum Qualifications

• B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.

Applicants should apply via The Mice Groups Inc. website (www.MiceGroups.com) or through this careers site posting.

We are an equal opportunity employer and value diversity at The Mice Groups Inc. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Pursuant to the San Francisco Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Pursuant to the Los Angeles Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

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