Summary

Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solvekey infrastructure challenges facing our customers.

We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment.We seek experienced verification engineerswho can contribute across the full lifecycle of complex chip development, from microarchitecture definitionto DV infrastructure and test development, to post-silicon testing.

Roles and Responsibilities

• Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage
• Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device
• Define and implement infrastructure for effective HW/SW co-simulation
• Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements
• The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms
  
  

Skills/Qualifications

• Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries
• Deep experience with full chip verification and infrastructure development
• Strong current knowledge of UVM constructs, components, and practices
• Expert knowledge of SystemVerilog, as well as Python or other scripting languages
• Experience with C/C++ and general software engineering principles is highly desirable
• Minimum BSEE/CE + 15 years or MSEE/CE + 10 years experience
• Proven track record of design execution and quality on products which have shipped in high-volume
  
  

Company Background

Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.

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