Role This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs. As a leader of this team, you will define verification methodologies, analyze problems, and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. You will have the opportunity to mentor junior members of the team. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems. Daily activity includes: Mentor/teach other verification members in their approaches Track schedule and project status Communication with team members to discuss technical details Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports Hands-on verification work including verification regression management, debugging and bug-reports Technical documentation Technical Requirements Bachelor’s or Master’s degree in related engineering field Proven track record for verifying designs to tape out quality Strong communication and leadership skills Experience using Verilog, System Verilog, UVM, coverage analysis, formal Strong mastery using Unix and scripting languages such as make, shell, perl or python Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) Desirable Skills Experience coding in assembly languages Strong desire to learn and willing to devote extra effort to achieve perfection Strong team player and possess a positive attitude Multi-lingual Cross-site or multi-time zone experience Good time management skills