Responsibilities Create or leverage existing testbenches to develop top level test bench using Verilog, SV, and UVM for a Communications Receiver ASIC Work with system architecture team and analog engineers to implement verification requirements in the test environment and test cases Create or update drivers, monitors, agents, probes and test patterns Create or update behavioral models for analog components Create and maintain test plans and use spreadsheets or other methods to track results Develop test cases, run RTL and gate simulations based on system scenarios, and debug failures Set up and run nightly regressions for RTL simulations and gate level simulations Report and coordinate all aspects of the verification tasks in all phases of the project Qualifications BS with 8+ years or MS with 7+ years of experience in digital verification. Degree should be in EE or CS or related field. Strong knowledge and experience using System Verilog and UVM Ability to integrate C models, matlab models, create scripts using Python, Tcl, or Perl Knowledge of Cadence tools for verification Willingness and ability to learn and contribute quickly Ability to work in collaboration with others Strongly desired - knowledge of digital signal processing, communications, C/C++, matlab