We are seeking a Design Implementation Engineer with over 2 years of experience to own the backend implementation of RISC-V cores and uncore blocks. The ideal candidate will be responsible for owning the Backend Convergence from synthesis to timing closure, and will work closely with RTL designers to ensure design closure.

Key Responsibilities

• Backend Implementation of RISC-V Cores and Uncore Blocks
• Implement the design through Synthesis, Place and Route, and Clock Tree Synthesis (CTS).
• UPF-based low-power design implementation.
• Scan insertion and timing closure to meet design requirements.
• Collaborate closely with RTL designers to address design gaps and ensure convergence.
• Analyze and resolve CDC, LINT, and Formality issues.
  
  

Design Understanding and Backend Convergence

• Develop a strong understanding of the design micro-architecture.
• Approach backend convergence with a focus on performance, power, and area (PPA) optimization.
  
  

Minimum Qualifications

• Bachelor’s degree in Electrical or Computer Engineering with 2+ years of relevant experience.
• Experience in backend design implementation, including synthesis, place and route, and CTS.
• Proficiency in UPF-based low-power design techniques.
• Familiarity with scan insertion, timing closure, and validation methods such as CDC, LINT, and Formality.
  
  

Preferred Qualifications

• Strong collaboration skills to work with RTL designers and cross-functional teams.
• Understanding of microarchitecture and its influence on backend design convergence.
• Experience with low-power design methodologies.
  
  

Here’s What You Can Expect From Us

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More About Us

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.