Meta is seeking an Engineering Manager to join our Silicon Enablement team. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure operates efficiently to deliver our innovative services. The Silicon Enablement team is responsible for the Hardware Lifecycle of all Meta servers including pre-production hands-on system and hardware debugging and stress testing, enabling production-ready system monitoring, automated provisioning and automated remediation of issues. The Silicon Enablement team work closely with hardware designers, system manufacturers, component vendors, capacity engineering, production engineering, Meta services, and data center operations teams to test systems before release to our production data centers, and to track the health and lifecycle of servers in production. The Silicon Enablement team primary charter is to deliver scalable and reliable custom ASIC solutions to meet Meta data center needs. Ramping to production and solving the datacenter scaling and deployment challenges requires us to take a systems based approach to Pre & Post Silicon Development and ValidationExperience in recruiting and managing technical teams, including performance management 10+ experience in ASIC Design, Development or Validation (Silicon bringup, validation, emulation, characterization) 3+ years of experience as a People Manager BS or advanced degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering, Math, Physics or a related field or equivalent experience Experience in leading strategic implementation and planning for risk and growth Developing and managing requirements, and making data-driven decisions Experience with current emulation technologies and methods, example simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, hybrid methods Experience leading teams in Emulation Track record of leadership in 'first-pass success' in ASIC where emulation is one of the key validation tools. Understanding of compilation and build flow with experience building images from scratch with necessary design modifications to adapt to emulation. Experience with verification, SoCs or similar designs. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip system) with an understanding of trade-offs between performance and ease of debug. Experience managing multiple design releases and working with cross functional teams to support and debug customer issues. Experience with SystemVerilog and C++ to model RTL components and transactors. Experience with post-silicon bring up, debug and reproducing issues on emulator. Experience with Palladium, Protium, or Zebu tools. Experience partnering with the design, verification, validation and software development teams.