Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.

• Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

• Responsible for on-time delivery of block-level layouts with acceptable quality.

• Excellent problem-solving skills in physical verification of custom layout.

• 5 + year’s experience in analog/custom layout design in advanced CMOS process.